Patents and Publications

I am a named inventor on over 30 U.S. patents and counting. My work has appeared under a few name variants over the years — Lisa Hsu, Lisa R. Hsu, and Lisa Ru-Feng Hsu. Canonical listings live on DBLP (Lisa Hsu), DBLP (Lisa R. Hsu), Google Scholar, and Justia Patents. Bolded names below indicate me.

Patents

A selection of granted U.S. patents on which I'm a named inventor. For the complete list (including pending applications), see Justia (Lisa R. Hsu) and Justia (Lisa Ru-Feng Hsu).

• Direct Swap Caching with Noisy Neighbor Mitigation and Dynamic Address Range Assignment H. Ballani, W. A. Saunders, C. L. Belady, L. R.-F. Hsu, P. Costa, D. M. Carmean, K. Shi, C. Boecker
  Microsoft · multiple grants/applications
• Wavefront Classification for Reducing Virtual Address Translation Latency in a Wide Execution Engine L. R. Hsu, J. M. O'Connor
  US Patent 11,301,256 · Advanced Micro Devices · 2022
• Memory Device System with Logic Die Operable in Slave or Host Modes N. S. Jayasena, G. H. Loh, B. M. Beckmann, J. M. O'Connor, L. R. Hsu
  US Patent 10,522,193 · Advanced Micro Devices · 2019
• Memory Access Pattern Monitor for Managing Shared Cache Resources J. Chung, S. Srikantaiah, L. Hsu
  US Patent 9,697,128 (and related) · Advanced Micro Devices · 2017
• Cache Replacement Policy Using Historical Eviction Information Inventors include L. Hsu
  US Patent 9,189,423 · Advanced Micro Devices · 2015
• Additional granted patents and pending applications See the Justia listings linked above for the complete enumeration.

Publications — 2020s

• Coach: Exploiting Temporal Patterns for All-Resource Oversubscription in Cloud Platforms B. Reidys, P. Zardoshti, Í. Goiri, C. Irvene, D. S. Berger, H. Ma, K. Arya, E. Cortez, T. Stark, E. Bak, M. Iyigun, S. Novakovic, L. Hsu, K. Trueba, A. Pan, C. Bansal, S. Rajmohan, J. Huang, R. Bianchini
  ASPLOS 2025
• Design Tradeoffs in CXL-Based Memory Pools for Public Cloud Platforms D. S. Berger, D. Ernst, H. Li, P. Zardoshti, M. Shah, S. Rajadnya, S. Lee, L. Hsu, I. Agarwal, M. D. Hill, R. Bianchini
  IEEE Micro 43(2), 2023
• Pond: CXL-Based Memory Pooling Systems for Cloud Platforms H. Li, D. S. Berger, L. Hsu, D. Ernst, P. Zardoshti, S. Novakovic, M. Shah, S. Rajadnya, S. Lee, I. Agarwal, M. D. Hill, M. Fontoura, R. Bianchini
  ASPLOS 2023 · Best Paper Award
• Hyrax: Fail-in-Place Server Operation in Cloud Platforms J. Lyu, M. You, C. Irvene, M. Jung, T. Narmore, J. Shapiro, L. Marshall, S. Samal, I. Manousakis, L. Hsu, P. Subbarayalu, A. Raniwala, B. Warrier, R. Bianchini, B. Schroeder, D. S. Berger
  OSDI 2023
• First-Generation Memory Disaggregation for Cloud Platforms H. Li, D. S. Berger, S. Novakovic, L. Hsu, D. Ernst, P. Zardoshti, M. Shah, I. Agarwal, M. D. Hill, M. Fontoura, R. Bianchini
  arXiv:2203.00241, 2022

Publications — 2010s

• Enabling Efficient Dynamic Resizing of Large DRAM Caches via a Hardware Consistent Hashing Mechanism K. K. Chang, G. H. Loh, M. Thottethodi, Y. Eckert, M. O'Connor, S. Manne, L. Hsu, L. Subramanian, O. Mutlu
  arXiv:1602.00722, 2016
• Address Translation for Throughput-Oriented Accelerators B. Pichai, L. Hsu, A. Bhattacharjee
  IEEE Micro 35(3), 2015
• Architectural Support for Address Translation on GPUs: Designing Memory Management Units for CPU/GPUs with Unified Address Spaces B. Pichai, L. Hsu, A. Bhattacharjee
  ASPLOS 2014
• A Case for a Flexible Scalar Unit in SIMT Architecture Y. Yang, P. Xiang, M. Mantor, N. Rubin, L. R. Hsu, Q. Dong, H. Zhou
  IPDPS 2014
• Exploiting Uniform Vector Instructions for GPGPU Performance, Energy Efficiency, and Opportunistic Reliability Enhancement P. Xiang, Y. Yang, M. Mantor, N. Rubin, L. R. Hsu, H. Zhou
  ICS 2013
• Characterizing and Evaluating a Key-Value Store Application on Heterogeneous CPU-GPU Systems T. H. Hetherington, T. G. Rogers, L. Hsu, M. O'Connor, T. M. Aamodt
  ISPASS 2012

Publications — 2000s

• Cache Resource Allocation in Large-Scale Chip Multiprocessors L. R. Hsu · Ph.D. dissertation, advisor Steven K. Reinhardt
  University of Michigan, 2009
• QoS Policies and Architecture for Cache/Memory in CMP Platforms R. R. Iyer, L. Zhao, F. Guo, R. Illikkal, S. Makineni, D. Newell, Y. Solihin, L. R. Hsu, S. K. Reinhardt
  SIGMETRICS 2007
• The M5 Simulator: Modeling Networked Systems N. L. Binkert, R. G. Dreslinski, L. R. Hsu, K. T. Lim, A. G. Saidi, S. K. Reinhardt
  IEEE Micro 26(4), 2006
• Earlier publications For the complete bibliography from graduate school through the AMD years, see the DBLP listings linked at the top of this page.